Prior art systems that include Single Inline Memory Module (SIMM) and Dual Inline Memory Module (DIMM) memory devices have two-bus structures. That is, one bus is used for data transfer (hereinafter the "data bus") and a second bus (hereinafter the "address/control bus") is used for address and control of individual memory components. Typically, Dynamic Random Access Memory (DRAM) semiconductor devices and Synchronous Dynamic Random Access Memory (SDRAM) devices are used as memory components.
Recent computer systems require more graphics capabilities and faster graphics performance. These computer systems which require advanced graphics capabilities have greatly increased the demand on the address/control bus. This is particularly true in systems that have unified graphics and system memory. Memory systems that have unified graphics and system memory require high performance address/control bandwidth, and low address/control latency. In addition, system memory applications require a broad range of memory component counts so as to allow a wide range of application configurations. Thus, high memory component capacity is required.
In order to meet the demands of unified graphics and system memory and 3D graphics requirements, some prior art memory systems use a buffer (hereinafter "address/control buffer"). These prior art memory modules typically include from four to eighteen memory components on each memory module. Though the use of an address/control buffer increases the apparent address/control bandwidth, it also gives high address/control signal latency.
Recent attempts to meet the demands of unified graphics and system memory and 3D graphics requirements include architectures that provide one-to-one correspondence of address versus data between the memory controller and each memory component. That is, the memory controller can address each memory component through a separate address/control connection. However, this type of memory system requires advanced electrical signaling levels. In addition, the number of memory components is limited by the capacity of the memory controller. That is, the direct one to one correspondence of address/control signals with data signals gives a signal count requirement that is too great for the memory controller to handle in high-end applications.
New graphics rendering engines require a new generation of addresses to memory components every memory clock period in order to achieve high 3D graphics performance. In addition, for 3D graphics applications it is desirable to address different parts of a memory word with unique addresses. This allows for access to unaligned data in a single memory clock period. This cannot be done using prior art memory systems and prior art memory modules. In addition, the large electrical length and loading of driving a prior art memory modules with a width of nine or more memory components gives a significant disruption to the electrical characteristics of the memory address/control signals supplied from the memory controller. This prevents transmission of address/control signals at the same rate as data signals.
Using prior art architectures, it is possible to achieve the needed address/control performance by limiting the memory components. However, by limiting the number of memory components, it is not possible to achieve the high count of memory components required for large system memory configurations. When intermediate address/control buffering is used between the memory controller and the memory components, the large capacity of memory components required for system memory is achievable. However the address/control buffering increases the latency to address and control the memory components, resulting in reduced graphics performance.
What is needed is a memory system and memory module that provides for high bandwidth addressing and control of memory components. In addition, a memory system and memory module that has low latency is required. Moreover, a memory system and memory module that does not require advanced electrical signaling is required. Furthermore, a memory system and memory module that has a high memory component capacity is required. Also, a memory system and memory module which may be addressed such that different parts of a memory word may be separately addressed with unique addresses is required so that unaligned data may be accessed in a single memory clock period. In addition, a memory system and memory module which allows for the transmission of address/control signals at the same rate as data signals is required. The present invention provides a simple, elegant solution to the above needs.